1. Field of the Invention
The present invention relates to a delay circuit for outputting an input signal delayed by exactly a predetermined delay time and to an oscillator circuit constituted by using the delay circuit, more particularly to a delay circuit controlling the delay time and oscillation frequency in accordance with a digital signal and to an oscillator circuit using the same.
2. Description of the Related Art
An example of a delay circuit in which the delay time can be freely set in accordance with a digital control signal is shown in FIG. 1. As illustrated, the delay circuit comprises n number of stages of delay elements DLY1, DLY2, . . . , and DLYn connected in series and an n-to-1 selection circuit SEL for selecting one among the n number of output signals from these delay elements and outputting the same. Each of the n number of stages of delay elements connected in series outputs a delay signal obtained by delaying an input signal by a predetermined time to the delay element of the next stage. The selection circuit SEL selects one from among the output signals of the n number of stages of delay elements in accordance with the digital control signal and then outputs the same.
For example, assuming that each delay element gives the same delay time t.sub.D to the input signal, by the delay circuit constituted as shown in FIG. 2, delay time of t.sub.D to nt.sub.D can be freely given with respect to an input signal.
An example of an oscillator circuit constituted by using the delay circuit is shown in FIG. 2. As illustrated, an inverter INV1 is provided in the delay circuit shown in FIG. 1, the output signal of the selection circuit SEL is input to the inverter INV1, and the output signal of the inverter INV1 is input as the input signal of the delay circuit to the delay element DLY1 of the initial stage. An oscillation signal (clock signal) CLK is obtained from the output terminal of the selection circuit SEL.
Namely, the oscillator circuit is constituted by a delay circuit comprised of elements connected in the form of a ring via the inverter. Since the oscillation frequency of the oscillator circuit is controlled by the delay time of the delay circuit, the frequency of the clock signal CLK can be controlled by controlling the delay time by a digital control signal.
Further, another example of an oscillator circuit controlling the oscillation frequency by a digital signal is shown in FIG. 3. The present example is constituted by a digital/analog converter (D/A converter) DAC and a voltage-controlled oscillator (VCO), the digital control signal is converted to an analog control voltage signal VC by the digital/analog converter DAC, and the oscillation frequency of the voltage-controlled oscillator VCO is controlled by the control voltage signal VC. By this, the frequency of the clock signal CLK generated by the voltage-controlled oscillator VCO can be controlled by a digital control signal.
FIG. 4 shows an example of an oscillator circuit changed in capacitance by a digital signal and controlling the oscillation frequency in accordance with the change of capacitance. As illustrated, the on/off state of switches SW0, SW1, SW2, . . . , and SWn is controlled in accordance with the digital signal. The total capacitance of the capacitance elements connected to the oscillator circuit OSC is controlled in accordance with this. Since the oscillation frequency of the oscillator circuit OSC is set in accordance with the capacitance of the connected capacitance elements, the frequency of the clock signal CLK obtained from the oscillator circuit OSC can be controlled by a digital control signal.
In the above-mentioned conventional digital control oscillator circuit, for example, the oscillator circuit shown in FIGS. 3 and 4, however, analog-like design elements are included. Therefore, there is a disadvantage that troublesome circuit design and correction are required taking into consideration the trade off between oscillation frequency range, linearity (linear characteristic) and the circuit scale etc. for every specification of the oscillator circuit and process of the LSI (large scale integrated circuit).
On the other hand, in a digital control oscillator circuit constituted by the selection circuit together with using usual gate circuits such as inverters and buffers as the delay elements, the circuit configuration, as shown in FIG. 2, is simple and then there are no analog-like elements, so the control of the frequency of the oscillation signal and the stability of the circuit operation are good. However, the delay time per stage of a usual delay element is large, therefore the step width of the frequency is large and it is difficult to finely set the oscillation frequency.
For example, where a delay element is constituted by two stage of inverters as shown in FIG. 5, an output terminal A of the inverter of the former stage constituted by a pMOS transistor PT1 and an nMOS transistor NT1 is connected to both of the gates of the pMOS transistor PT2 and nMOS transistor NT2 constituting the inverter of the latter stage, the load of the inverters become large, and the operation speed is lowered. Further, as shown in the waveform diagram of FIG. 6, the threshold voltage of the usual inverter is a half of the power supply voltage VDD, the output signal level of the inverter changes around a time when the level of the input signal becomes substantially VDD/2, therefore the delay time t.sub.D per stage of inverter becomes large.